1. Field of the Invention
The present invention relates to semiconductor memory devices employing Built-In-Self-Test (BIST), and particularly, to a novel BIST system and method for calculating redundancy for a two-dimensional redundancy scheme.
2. Description of the Prior Art
Redundancy is required on all large semiconductor memories to ensure adequate chip yield. Memories are very dense circuits and are sensitive to subtle defects to which logic circuits are immune. Thus yield is improved by including redundant elements to replace defective memory portions. As an example, it is not unusual for a chip yield to be 25% without redundancy, 50% with row redundancy, and 70% with two-dimensional (row and column) redundancy. Further, it is not unusual to see very low yields with insufficient redundancy, sometimes below 1%.
Most memories today are embedded so that the memory inputs and outputs (I/O) do not come to the chip I/O. For these memories built-in self-test (BIST) is employed to do the testing and also calculate the needed redundancy replacement. Calculating redundancy replacement is easy on stand-alone memories since all the failing locations can be recorded at the tester followed by selection of optimal redundancy implementation. When BIST is employed, as is required in microprocessors and ASICS, the redundancy calculation must be determined on the fly since there is insufficient space to store all the failing locations prior to selecting the redundancy implementation.
Most SRAMs with redundancy have only had a single dimension of redundancy that is implemented with spare rows. When a failure is seen during test on a given word, the row which that word is part of gets replaced with a redundant row. That way all words which are in that row are replaced. This works well with BIST since a single pass/fail signal can be sent back from the memory to the BIST on each read.
FIG. 1 depicts an example BIST pass/fail compare circuit 10 including a simple XOR-OR tree 20 that functions to compare the memory word (e.g., 72-bits) output from a row of memory 15 with the expected data output from the BIST 25. This is accomplished local to the memory 15 and the resulting pass/fail signal generated by the tree 30 is sent back to the BIST 25, where the redundancy calculation is stored.
Two-dimensional redundancy has been implemented on DRAMs, SRAMs, and CAMs when required, but is not widely utilized unless absolutely needed, due to the required overhead. FIG. 2 illustrates an example BIST pass/fail compare circuit 50 including an XOR tree 55 that functions to compare the memory word (e.g., 72-bits) output from a row of memory 65 with the expected data output from the BIST 26. This prior art BIST pass/compare scheme however, includes added counter devices 75, that, on a per bit basis, enable a column redundancy calculation. That is, when a failure is encountered, where column redundancy is available, the bit location within the word is determined. Thus, for a 72-bit word, for example, the results 56 of each of the 72 bit comparisons are accumulated across multiple reads, requiring the counters 75 shown in FIG. 2 in addition to the OR circuitry shown in FIG. 1. These counters 75 are then unloaded to determine the correct redundancy implementation after reaching the top of the columns being tested. Obviously, the amount of circuit overhead to implement these many counters 75 (e.g., approximately 4700 cells for the needed counters and associated clock splitters, etc.), along with the logistical problem of unloading the counters before continuing the BIST testing, create challenges.
Another alternative is to unload each fail to an external tester so that the tester can calculate the redundancy. This requires much more test time since the information must be sent off chip for each fail. It also decreases the test quality by having to stop test for each fail rather than providing back-to-back at-speed tests. The other alternative is to accumulate fails along a column with a counter to determine when column redundancy is required. This requires much more space on chip and requires that the result be implemented prior to determining proper row redundancy.